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Description: DPLL由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.
整个系统的中心频率(即signal_in和signal_out的码速率的2倍)
为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.-DPLL phase detector by the addition and subtraction counter modulus K synchronous pulse addition and subtraction circuit detection circuit establishing mode N divider constituted. The entire system of the center frequency (ie signal_in and signal_out the code rate of 2 times) for clk/8/N. Modulus K addition and subtraction of the K value of Counter DPLL decision accuracy and synchronization set-up time, K the greater the synchronization set-up time is long, synchronous and high accuracy. In contrast the short and low.
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Description: Phase Based Template Matching: Phase information is used for matching the input imagery with the template. Both the images are filtered with canny edge detector. The timing efficiency is introduced by implementing skipping steps while doing correlation. The advantage of Phase based correlation technique is that it shows good response against shift/brightness variation and noise addition i.e. salt & pepper/Gaussian noise [1,2]. Templates includes small portion of cropped from input imagery with gaussian noise introduced in them.
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Size: 71680 |
Author: zhangxq |
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Description: protel99图 电机相位检测板应用于电机的转速检测和相位检测-Figure protel99 board phase detector used in electric motor speed detection and phase detection
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Size: 99328 |
Author: fanhoufa |
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Description: 小学期的源程序
1．试编MATLAB程序。信号 sinc(10*t),-2<=t<=2
m(t)=
0,其它
用100hz的载波来产DSB信号并解调。完成下列工作：
画出已调信号；
求已调信号的频谱，并用图像表示。
画出解调信号；
求解调信号的频谱，并用图像表示。
2．信号
sinc2(100t),|t|≤t0
m(t)=
0, 其它
采用频率调制调制为1000HZ的载波。频偏常数为kf=50,t0=0.2。
注：（求和代替积分）
3．信号
2, t0/3>t>0
m(t)= -6, t0/3<=t<2*t0/3
0, 其它
t0=0.15,使用AM调制和包络检波解调.-Primary phase of source 1. Test procedures for MATLAB. Signal sinc (10* t),-2 < = t < = 2 m (t) = 0, the other with the 100hz signal carrier to the middle class and DSB demodulation. To complete the following tasks: Draw has been transferred signal for the spectrum signals have been adjusted, and image representation. Draw demodulation signal solving transfer spectrum signal, and image representation. 2. Signal sinc2 (100t), | t | ≤ t0 m (t) = 0, the other the use of frequency modulation of the carrier modulation for 1000HZ. Offset constant kf = 50, t0 = 0.2. Note: (sum in lieu of points) 3. Signal 2, t0/3> t> 0 m (t) =-6, t0/3 < = t < 2* t0/3 0, other t0 = 0.15, the use of AM modulation and demodulation envelope detector.
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Size: 3072 |
Author: 张静 |
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Description: 使用labview7.1编写的一个简单的虚拟电能质量检测仪，监测参数包括电压偏差、频率偏差、频域谐波分析、电压波动、三相不平衡度等。-Labview7.1 prepared using a simple detector of virtual power quality, monitoring parameters, including voltage deviation, frequency deviation, frequency-domain harmonic analysis, voltage fluctuations, such as three-phase imbalance.
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Size: 61440 |
Author: robyluo |
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Description: ADF4157是ADI公司出品的一款锁相环芯片，它含有一个鉴相器，一个电子泵，一个sigma delta 分频器-ADI Corporation ADF4157 is a production of the chip phase-locked loop, which contains a phase detector, an electronic pump, a sigma delta prescaler
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Size: 350208 |
Author: sherry |
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Description: 自己做的测频测相器（硬件使用EPM240采样计数mega16取数和控制），此为EPM240的程序，使用quartus编程，主要包含两个接近20位的计数器。-This is the frequency and phase detector (hardware using EPM240 sampling and counting, mega16 take the number and control), this is EPM240 procedures, using quartus programming consists mainly of two nearly 20-bit counter.
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Size: 177152 |
Author: 黎鑫 |
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Description: 自己做的测频测相器（硬件使用EPM240采样计数mega16取数和控制），此为Emega16的程序，使用ICCAVR编程，主要包含测频和测相的计数值的处理，和LCD12864的显示-This is frequency and phase detector(hardware using EPM240 sample count mega16 take the number and control), this is Emega16 procedures, the use of ICCAVR programming consists process of count number of frequency and phase detector, and the display of LCD12864
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Size: 50176 |
Author: 黎鑫 |
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Description: 此为我们组在学校比赛中设计的多功能计数器的系统设计文档，此多功能计数器即是测频测相器（硬件使用EPM240采样和计数，mega16取数和控制）-This is our group s multi-purpose counter system design documents in school competitions. This multi-function counter that is the frequency and phase detector(hardware using EPM240 sampling and counting, mega16 take the count number and control).
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Size: 463872 |
Author: 黎鑫 |
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Description: 此为我们组在学校比赛中设计的多功能计数器的系统设计文档，此多功能计数器即是测频测相器（硬件使用EPM240采样和计数，mega16取数和控制）-This is our group s multi-purpose counter system design documents in school competitions. This multi-function counter that is the frequency and phase detector(hardware using EPM240 sampling and counting, mega16 take the count number and control).
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Size: 463872 |
Author: 黎鑫 |
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Description: musicdsp source code archive-Analysis
Beat Detector Class
Coefficients for Daubechies wavelets 1-38
DFT
Envelope detector
Envelope Detector class (C++)
Envelope follower with different attack and release
Fast in-place Walsh-Hadamard Transform
FFT
FFT classes in C++ and Object Pascal
Frequency response from biquad coefficients
Java FFT
Look ahead limiting
LPC analysis (autocorrelation+ Levinson-Durbin recursion)
Magnitude and phase plot of arbitrary IIR function, up to 5th order
Measuring interpollation noise
QFT and DQFT (double precision) classes
Simple peak follower
tone detection with Goertzel
Tone detection with Goertzel (x86 ASM)
Effects
2 Wave shaping things
Alien Wah
Band Limited PWM Generator
Bit quantization/reduction effect
Class for waveguide/delay effects
Compressor
Decimator
Delay time calculation for reverberation
DIRAC- Free C/C++ Library for Time and Pitch Manipulation of Audio Based on Time-Frequency Transforms
dynamic convolution
Early echo s with image-mirror techn
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Size: 826368 |
Author: Alan Tang |
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Description: DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成.
整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.
-DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, synchronous detection circuit established, constitute a model N divider. The whole system of the center frequency (ie signal_in and signal_out the code rate of 2 times) to clk/8/N. modulus K K value addition and subtraction counter DPLL decision to establish the accuracy and synchronization time, K is larger, the simultaneous establishment of a long time, synchronization accuracy. contrary is short and low.
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Size: 1024 |
Author: 鬼舞十七 |
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Description: 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programming,
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Size: 19456 |
Author: 生活的 |
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Description: 基于ISE的鉴频、鉴相器，开发板：xilinx公司spartan 3E 500.精确度1hz,1度。完全正确。-Based on ISE' s Kam-frequency phase detector, development board: xilinx company spartan 3E 500. Precision 1hz, 1 degree. Entirely correct.
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Size: 21100544 |
Author: aaaajjjj |
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Description: C51 实现的相位检测，带PROTEUS仿真-C51 implementation phase detection, with PROTEUS simulation
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Size: 141312 |
Author: czz |
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Description: it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm and the test bench of it.
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Size: 5120 |
Author: syamprasad |
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Description: 搭建pll电路，主要包括鉴相器，低通滤波器，压控振荡器，包括个部分的输出信号-Pll circuit structures, including phase detector, low pass filter, VCO, including a part of the output signal
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Size: 7168 |
Author: 陈力 |
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Description: Quartus的鉴相器硬件电路设计 Quartus的鉴相器硬件电路设计
-Quartus the hardware design phase detector phase Quartus' s Quartus hardware circuit design of hardware circuit design phase
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Size: 4572160 |
Author: gudaoping |
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Description: 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
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Size: 798720 |
Author: taotao |
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Description: 数字锁相环频率合成器的设计，数字鉴相器，数字滤波器，数控振荡器，反馈分频器-Digital PLL frequency synthesizer, digital phase detector, digital filter, digital control oscillator, the feedback divider
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Size: 798720 |
Author: taotao |
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